Computer ScienceCore26 min read

CPU Architecture and Parallel Processing

What is inside the processor, and why one instruction takes several steps

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01

The von Neumann idea

The design almost every computer still uses was set out in 1945, and its central idea is that programs and data are stored in the same memory. Before that, machines were rewired to change what they did. Storing the program as data meant a machine could be reprogrammed by loading different numbers — which is what made general-purpose computing possible.

It also creates the architecture's main weakness. Instructions and data travel along the same bus, so they cannot move at the same time. The processor spends much of its life waiting for memory, a limitation known as the von Neumann bottleneck.

ComponentWhat it does
ALUperforms arithmetic and logical operations
Control unitdecodes instructions and issues control signals
Program counter (PC)holds the address of the NEXT instruction
Memory address register (MAR)holds the address currently being accessed
Memory data register (MDR)holds the data or instruction just fetched
Current instruction register (CIR)holds the instruction being decoded
Accumulator (ACC)holds the working result of calculations
Status registerholds flags set by the last operation

The three buses, and which way they run

The address bus is unidirectional — addresses only ever travel from the processor to memory. The data bus is bidirectional, since data moves both ways. The control bus carries timing and command signals and is also bidirectional. A frequent question asks for the direction of each and the reason, and the address bus is the one that must be one-way.

02

The fetch–decode–execute cycle

A processor does not execute an instruction in one action. It repeats a fixed cycle: collect the next instruction from memory, work out what it means, then carry it out. That cycle runs billions of times per second and never varies in structure.

Tracing it in terms of registers is a standard exam task, and the wording matters — each step must name the registers involved rather than describing the effect loosely.

FETCHPC → MARaddress of next instructionPC incrementedready for the following onememory[MAR] → MDRinstruction read outMDR → CIRmoved for decodingDECODEcontrol unit interprets the opcode in the CIREXECUTEthe operation is carried out; ACC often updatedthe PC is incremented during the fetch, before execution
PC
program counteraddress of the NEXT instruction, not the current one
MAR
memory address registerthe address being accessed right now
MDR
memory data registerwhatever was just read from or is going to memory
CIR
current instruction registerholds the instruction while it is decoded

Step through and watch the registers change. Notice that the program counter is incremented before the instruction is executed, not after — which is exactly why a jump instruction can overwrite it and still work correctly.

Why the increment happens early

If the PC were incremented after execution, a jump instruction that had just written a new address into the PC would then have that address incremented — and the jump would land one instruction too far. Incrementing during the fetch means a jump simply overwrites the PC afterwards and works correctly. Questions about jumps almost always hinge on this ordering.

03

What makes a processor faster

Four factors are examined, and the useful thing is that each has a limit — which is why raw clock speed stopped rising years ago.

Clock speed sets how many cycles occur per second, but higher speeds generate heat that becomes impractical to remove. Cache is small, very fast memory close to the core holding recently used data; more cache reduces waiting on main memory, but it is expensive per byte. Word length and bus width determine how much moves at once — a wider data bus carries more per transfer, and a wider address bus can address more memory.

Since clock speed hit a thermal ceiling, manufacturers added cores instead. Two cores can genuinely execute two instructions at the same moment, but only if the software is written to divide the work — which is why a single-threaded program runs no faster on an eight-core machine.

ChangeEffectIts limit
higher clock speedmore cycles per secondheat becomes unmanageable
more cacheless waiting on main memoryexpensive, and diminishing returns
wider data busmore data per transferphysical pin count and cost
wider address busmore memory addressablerarely the bottleneck now
more coresgenuine parallel executionsoftware must be written for it
04

Parallel processing and virtual machines

Parallel systems are classified by whether the instructions and the data are single or multiple. SISD is the traditional single processor. SIMD applies one instruction to many data items simultaneously, which is what a graphics processor does to millions of pixels. MIMD runs different instructions on different data, which is what a multi-core CPU does.

A virtual machine is software that behaves like a physical computer. One physical machine can run several, each with its own operating system, isolated from the others. This is how cloud hosting works, and how a single server is shared between customers who never see one another's data.

The trade-off is straightforward: virtual machines give isolation, easy backup and efficient use of hardware, at the cost of some performance, since everything passes through an extra software layer.

Points that come up repeatedly

  1. Von Neumann stores programs and data in the same memory — that is the whole idea.
  2. The bottleneck exists because instructions and data share one bus.
  3. The PC holds the address of the next instruction and is incremented during the fetch.
  4. The address bus is one-way; the data and control buses are two-way.
  5. More cores help only if the software divides the work between them.
  6. SIMD suits graphics; MIMD suits general multi-core work.
  7. A virtual machine trades some speed for isolation and better hardware use.

Practice questions

5 questions · 15 marks · full working on every one

Try each one on paper first, then open the working. The marks are shown where they are actually awarded, because that is where they are actually lost.

Short questions

4 · 9 marks

Two marks each, in the style of the short-question section of the paper. Answer in two or three lines.

SQ1[2 marks]
State what is meant by the von Neumann architecture and identify one limitation of it.
Model answer

In the von Neumann architecture, program instructions and data are held in the same memory and travel over the same bus. The limitation is the von Neumann bottleneck: instructions and data cannot be transferred simultaneously, so the processor is often left waiting for memory.

Examiner tip. One mark for the shared memory, one for the bottleneck. Naming the bottleneck without explaining it is usually not enough.

SQ2[3 marks]
Describe the fetch stage of the fetch–decode–execute cycle, naming the registers used.
Model answer

The address in the PC is copied to the MAR. The PC is then incremented. The contents of the memory location addressed by the MAR are read into the MDR, and from there the instruction is copied into the CIR ready for decoding.

Examiner tip. Three marks for four steps, so name every register. The increment is a step in its own right and is frequently omitted.

SQ3[2 marks]
Explain why the program counter is incremented during the fetch stage rather than after execution.
Model answer

A jump instruction writes a new address into the PC during execution. If the increment happened afterwards, that new address would be increased by one and the jump would land at the wrong instruction. Incrementing during the fetch means a jump can simply overwrite the PC and execution continues correctly.

Examiner tip. The answer must reference jump instructions — that is the whole reason for the ordering.

SQ4[2 marks]
Distinguish between SIMD and MIMD, giving a typical use of each.
Model answer

SIMD applies a single instruction to multiple data items at the same time — used by graphics processors operating on many pixels identically. MIMD executes different instructions on different data simultaneously — used by multi-core processors running separate tasks.

Examiner tip. One mark for the distinction, one for appropriate examples of each.

Exam questions

1 · 6 marks

Multi-part questions with a full mark scheme.

Q1[6 marks]
(a) State the direction of data flow on the address bus and on the data bus, giving a reason for the address bus.
(b) Explain how increasing cache size can improve performance.
(c) A program runs at the same speed on a four-core processor as on a single core. Explain why.
(d) State one advantage and one disadvantage of using virtual machines.
Mark scheme
  1. (a) The address bus is unidirectional; the data bus is bidirectional.Both directions must be stated.[1]
  2. The address bus is one-way because only the processor generates addresses — memory never sends one back.The reason is the mark, not the direction alone.[1]
  3. (b) Cache is faster than main memory and holds recently or frequently used data, so more requests are met without a slow main-memory access.The speed difference must be mentioned.[1]
  4. This reduces the time the processor spends idle waiting for data.Linking to the bottleneck earns the second mark.[1]
  5. (c) The program is single-threaded, so the work is not divided between cores and only one core is used.The software, not the hardware, is the limitation.[1]
  6. (d) Advantage: several isolated systems on one machine, using hardware efficiently. Disadvantage: slower than running directly on hardware, because of the extra software layer.One of each is required.[1]

(a) address one-way, data two-way; (b) fewer slow memory accesses; (c) single-threaded; (d) isolation vs overhead